1. Field of the Invention
The present invention relates to a booster circuit.
2. Description of Related Art
FIG. 14 shows a positive potential booster circuit 1 in accordance with a related art. As shown in FIG. 14, the booster circuit 1 includes PMOS transistors MP1 and MP2, a capacitor C1, level shifters LS1 and LS2, and an amplifier AMP1. The PMOS transistor MP1 is connected between a supply voltage terminal VDD and a node N1. To the gate of the PMOS transistor MP1, an output signal of the level shifter LS1 is provided. The PMOS transistor MP2 is connected between the node N1 and a node N2. To the gate of the PMOS transistor MP2, an output signal of the level shifter LS2 is provided.
The level shifter LS1 receives a clock signal CLK1, and provides an output clock signal to the gate of the PMOS transistor MP1. The level shifter LS1 is supplied with a high-potential supply voltage from the node N1 and supplied with a low-potential supply voltage from a ground terminal GND. The level shifter LS2 receives a clock signal CLK2, and provides an output clock signal to the gate of the PMOS transistor MP2. The level shifter LS2 is supplied with a high-potential power supply from an output terminal OUT1 and supplied with a low-potential power supply from a ground terminal GND. Note that, for the sake of convenience, the reference characters “VDD” and “GND” not only denote the names of the terminals, but also denote the voltages supplied from the terminals. The voltage of the output terminal OUT1 is denoted by VOUT.
One end of the capacitor C1 is connected to the output of the amplifier AMP1, and the other end of the capacitor C1 is connected to the node N1. The amplifier AMP1 receives a clock signal CLK3, and provides an output clock signal to the one end of the capacitor C1. Note that, the amplifier AMP 1 is supplied with a high-potential power supply from a supply voltage terminal VDD and supplied with a low-potential power supply from a ground terminal GND.
FIG. 15 is a timing chart that shows the operation of the booster circuit 1. As shown in FIG. 15, during the period from time points t1 to t2, the clock signal CLK1 is at low level and the PMOS transistor MP1 is in ON state. Hence, the supply voltage terminal VDD and the node N1 are electrically connected to each other, causing the potential of the node N1 to be the supply voltage VDD. On the other hand, since the clock signal CLK3 is at low level during this period, the potential of the one end of the capacitor C1 is the ground voltage GND, and the capacitor C1 is charged.
During the period from time points t3 to t6, the clock signal CLK3 is at high level, and the potential of the other end of the capacitor C1 is the supply voltage VDD. This boosts the potential of the one end of the charged capacitor C1, and causes the potential of the node N1 to be 2 VDD. During the period from time points t4 to t5, the clock signal CLK2 is at low level, and the PMOS transistor MP2 is in ON state. Hence, the node N1 and the output terminal OUT 1 are electrically connected to each other, causing the output voltage VOUT to be 2VDD.
Here, during the period from time points t3 to t6, the potential of the node N1 is 2VDD. Therefore, in order to prevent backflow of current at the supply voltage terminal VDD, it is necessary to turn off the PMOS transistor MP1 during the period from time points t2 to t6. Hence, the level shifter LS1 structured as shown in FIG. 16 is used for turning off the PMOS transistor MP1 during the period from time points t2 to t6.
FIG. 16 shows the detailed circuit structure of the level shifter LS1. Note that the level shifter LS2 is similarly structured. The level shifter LS1 includes PMOS transistors MP11 and MP12, NMOS transistors MN11 and MN12, an input terminal IN10, output terminals OUT10 and OUT10B, and an inverter circuit IV10.
The PMOS transistor MP11 is connected between the node N1 and the output terminal OUT10B. The gate of the PMOS transistor MP11 is connected to the output terminal OUT10. The PMOS transistor MP12 is connected between the node N1 and the output terminal OUT10. The gate of the PMOS transistor MP12 is connected to the output terminal OUT10B. The NMOS transistor MN11 is connected between the output terminal OUT10B and a ground terminal GND. The gate of the NMOS transistor MN11 is connected to the input terminal IN10. The NMOS transistor MN12 is connected between the output terminal OUT10 and the ground terminal GND. The gate of the NMOS transistor MN12 is connected to the output terminal of the inverter circuit IV 10.
FIG. 17 shows a table representing the relationship between the clock signal CLK1 received at the input terminal IN10 and the potential of the output terminal OUT10 (and that of the inverted output terminal OUT10B) of the level shifter LS1. As can be seen, when the clock signal CLK1 is at low level (when “L” in the table), the output of the level shifter LS1 is a potential of the ground voltage GND; when the clock signal CLK1 is at high level (when “H” in the table), the output of the level shifter LS1 is a potential of 2VDD.
Here, the potential difference between the high level power supply of the level shifter LS1 and the low level power supply of the same is 2×VDD. Therefore, the PMOS transistors MP11 and MP12 and the NMOS transistors MN11 and MN12 must be structured with high-voltage transistors that can withstand a potential difference twice as great as the supply voltage VDD. However, a high-voltage transistor requires a thickened gate oxide film. The thicker the gate oxide film, the greater the required channel length. Hence, such a thick-film transistor poses a problem of an increased layout area.
FIG. 18 shows the structure of a booster circuit 2 that generates a negative voltage −VDD. As shown in FIG. 18, the booster circuit 2 includes NMOS transistor MN1 and MN2, a capacitor C1, level shifters LS3 and LS4, and an amplifier AMP1. The operation timing chart of the booster circuit 2 is basically similar to that shown in FIG. 15 except for the polarity of the booster circuit 1 and, therefore, it is omitted. FIG. 19 shows the structure of the level shifter LS3 (and that of LS4). FIG. 20 is a table showing the relationship between the clock signal CLK1 received at the input terminal IN10 and the potential of the output terminal OUT10 (and that of an inverted output terminal OUT10B) of the level shifter LS3. Similarly to the level shifter LS1, in the level shifter LS3 also, the potential difference between the high level power supply and the low level power supply is 2×VDD. Therefore, the PMOS transistors MP11 and MP12 and the NMOS transistors MN11 and MN12 must be structured with high-voltage transistors.
One exemplary booster circuit in accordance with prior art is disclosed in Japanese Unexamined Patent Application Publication No. 2005-129815. However, the technique disclosed therein is also based on use of high-voltage transistors, similarly to the booster circuit 1.